1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing advanced programmable interrupt control circuitry for use with Intel microprocessors having associated embedded hardware.
2. History of the Prior Art
Historically, computers utilizing microprocessors manufactured by Intel Corporation of Santa Clara, Calif., such as the 8088, 8086, 80186, 80286, i386.TM., and i486.TM. (herein referred to as Intel processors) have included an Intel 8259 programmable interrupt controller (PIC) or an interrupt controller patterned thereon. This interrupt controller provides interrupt signals to an associated processor for various hardware devices associated with the processor. The priority level of an interrupt provided by these controllers is fixed for each hardware device and depends on the input pin position on the PIC where the particular hardware device from which the interrupt signal emanates is connected. That is, an interrupt from the keyboard is always transferred to the processor by the interrupt controller at a certain priority level while an interrupt from another hardware device is transferred to the processor by the controller at another priority level. These priority levels are hardwired and remain constant throughout the operation of the device. In systems using multiple processors, such an interrupt controller is capable of furnishing interrupts to only a single one of the processors. Consequently, it has been necessary to provide software solutions to control the inter-relation of interrupts in systems using many processors.
With more advanced computer systems running advanced operating systems, it is desirable to be able to change the priority level at which interrupt signals from a particular hardware component are handled as the circumstances of operation change. That is, a particular interrupt may be very important in certain instances and less important in other circumstances. Therefore, it is desirable that the priority levels of particular hardware be programmable.
Moreover, the operation of a computer system depends on the correct interrelation between the operation of the hardware and the software. Consequently, interrupt priority levels associated with the software processes and interrupts from hardware devices should be coordinated and made programmable so that the use of interrupts may depend on the circumstances of the computer system operation. More advanced operating systems provide for this coordination of hardware and task interrupt priority levels. In addition, it is desirable that all of the interrupts in a system utilizing multiple processors be coordinated so that a processor may provide interrupts to other processors to effect the best use of software it is running and so that a processor which is the least utilized may handle an interrupt for another processor without the need to accomplish this by the use of software control.
Recently, a new interrupt controller has been designed which is capable of accomplishing these desirable features, among others. Intel Corporation markets this interrupt controller as the 82489DX Advanced Programmable Interrupt Controller (APIC). This controller provides multiprocessor interrupt management which includes programmable interrupts for both tasks and devices. This controller also has facilities for transferring interrupts between processors and to the least used one of a plurality of processors used in a multiprocessor system. Such a controller is described in detail in a publication entitled 82489DX Advanced Programmable Interrupt Controller, published by Intel Corporation of Santa Clara, Calif.
However, the great majority of existing Intel processors utilize 8259 type PIC interrupt controllers. The system software is written to utilize these PIC interrupt controllers. A large number of application programs which are used extensively are run on these operating systems that do not utilize the newer Intel APIC controller. Instead these processors and systems provide interrupts based on the presence of the older PIC controller. In order to utilize existing Intel processors in advanced computer systems which include the newer APIC interrupt controllers to obtain the advantages these newer interrupt controllers offer, it has been necessary to devise circuitry which incorporates both controllers and to modify the system software to run with this hybrid system of interrupt controllers. In this hybrid interrupt controller system, the system basic input/output start up (BIOS) routines programs the APIC controller upon initialization of the circuitry; and the hybrid system software handles the PIC controller during operation so that the two controllers may operate together.
The simplest arrangement for combining the controllers connects the hardware devices which utilize the PIC controller to fixed pins of that controller and provides the output of the PIC controller as one of the input pins of the new APIC controller. Since the hardware interrupts provided by the PIC controller will vary from lowest to highest priority, it is necessary that the APIC controller receiving an interrupt for these devices to treat that interrupt as always of the highest priority. The ultimate effect of this arrangement is always to give the hardwired device interrupts connected to the PIC controller the highest priority and to make them non-programmable with respect to new interrupts and to various software process interrupts. This has the effect of slowing the operation of controlling interrupts to that at which the older interrupt controller works and obviates most of the advantages obtained by including the new controller.
Another arrangement for the two controllers connects the hardware devices which utilize the PIC controller to fixed pins of that controller but also provides these inputs to the APIC controller. This allows the hardware interrupts which are routed around the PIC controller to be individually programmable by the new APIC controller. However, if any hardware devices are embedded in the same circuitry (in the same chipset) as the controller and do not allow touting the interrupts around the controller, these interrupts must still be provided to the APIC controller as the output of the PIC controller on one of the input pins to the APIC controller. Since the particular interrupt is unknown to the APIC controller and because the interrupts provided by the PIC controller will vary from lowest to highest priority, it is necessary that the APIC controller receiving such an interrupt also treat that interrupt as always of the highest priority. The ultimate effect of this arrangement is always to give the hardwired device interrupts connected to the PIC controller the highest priority and to make them non-programmable with respect to new interrupts and to various software process interrupts. As with the other arrangement, this has the effect of slowing the operation of controlling interrupts to the speed at which the older interrupt controller works and obviates most of the advantages obtained by including the new controller.